To prevent integrated circuits from damage by electrostatic discharge (ESD) events, certain measures must be taken either in the package of a chip or directly on the chip. On-chip protection can be achieved by adhering to ESD specific layout rules, by an optimized process, and by placing ESD protection devices, which directly protect endangered circuits. ESD protection devices establish low-ohmic discharge paths during an ESD event thus keeping high voltages and currents away from the functional circuit elements of the IC.
ESD protection concepts in CMOS technologies are often based on specially designed ESD protection devices such as gate grounded NMOS transistors (ggNMOS), diode strings or SCRs (silicon controlled rectifiers) with trigger elements. In certain cases, none of these devices can be used as a protection element. The most prominent cases are high voltage requirements if only low voltage devices are available. For example, if only thin or medium gate oxides can be used, the standard ggNMOS based on the thick gate oxide is not available for ESD protection.
For the cases described above, there is no good solution based on the usual ESD devices. Neither ggNMOS nor SCRs with trigger elements can be used if there is no thick oxide available. At first sight, stacked NMOS devices might represent a solution but they suffer from severe drawbacks such as holding voltages that are too high and ESD hardness that is too low. In conventional CMOS technologies, lateral bipolar transistors (npn or pnp) are also not suited due to their rather high threshold voltages.